FULLY REMOTE- Design Verification Engineer-SystemVerilog UVM
Company: CyberCoders
Location: Garland
Posted on: August 6, 2022
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Job Description:
If you are a FULLY REMOTE- Design Verification
Engineer-SystemVerilog UVM with experience, please read on!
What You Will Be Doing
THESE POSITIONS ARE FOREVER FULLY REMOTE, I HAVE POSITIONS FROM MID
LEVEL TO PRINICPAL LEVEL FOR THIS ROLE
Job Title: Design Verification Engineer of SOC
Skills in ASIC / FPGA verification (directed test or SystemVerilog
/ UVM)
Basic knowledge in design techniques Verilog or VHDL
Good knowledge of simulation flow
Good basis in scripting Python, Perl, Bash&
A good level in English, both writing and oral skills
Humanly, you have to be rigorous and have a good analytical mind,
you have to enjoy working in a team and being diplomatic, in
particular when you have to point out the bugs discovered.
What You Need for this Position
So, if you are a FULLY REMOTE- Design Verification
Engineer-SystemVerilog UVM with experience, please apply today!
Email Your Resume In Word To
Looking forward to receiving your resume through our website and
going over the position with you. Clicking apply is the best way to
apply, but you may also:
Jonathan.Gilmor@CyberCoders.com
Jonathan Gilmor - Recruiting Manager - CyberCoders
Applicants must be authorized to work in the U.S.
CyberCoders, Inc is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment
without regard to race, color, religion, sex, national origin,
disability, protected veteran status, or any other characteristic
protected by law.
Your Right to Work - In compliance with federal law, all persons
hired will be required to verify identity and eligibility to work
in the United States and to complete the required employment
eligibility verification document form upon hire.
Keywords: CyberCoders, Garland , FULLY REMOTE- Design Verification Engineer-SystemVerilog UVM, Engineering , Garland, Texas
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here to apply!
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