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Principal Verification Lead

Company: SBT
Location: Garland
Posted on: April 5, 2021

Job Description:

Does making the next great technology product excite you? Imagine what you could do at a startup. At a startup, your new ideas will have a quicker road to becoming great products, services, and customer experiences. However, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the "extra mile" to achieve unthinkable results.
Design Engineer:Our client is looking for exceptional Processor Architects who have a passion for solving hard problems and enjoy bringing complex systems to life and take advantage of learning and career progress that can be achieved at early stage companies.
Responsibilities:

  • The architecture of processor & IP blocks including aggressive optimization for performance, power, and area.
  • Implementation of IP and SOC RTL logic in Verilog
  • Occasional verification of IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, emulation, etc.
  • Performance and power verification and validation of IP and SOC
    Qualifications:
    • MSEE / Ph.D. in Electrical Engineering with 7+ years of relevant Processor Design experience
    • Expert knowledge of Verilog and VHDL plus excellent programming skills
    • Solid understanding of Processors and complex SoCs.
    • High preference to high-speed interfaces like GPU, PCIe, network-on-a-chip, GPU & CPU
    • Knowledge and understanding of the full ASIC design flow, including synthesis, P&R
      Verification Engineer:Our client is looking for exceptional verification engineers who have a passion for solving hard problems and enjoy bringing complex systems to life and take advantage of learning and career progress that can be achieved at early stage companies.
      Successful Candidate For This Position Will Have
      • MSEE or Ph.D. and 7+ Years design verification experience with expertise in testbench architecture (SystemVerilog or Verilog based)
      • Familiarity with industry standard verification methodologies like coverage, OVM/UVM and Objected Oriented Programming
      • Knowledge of SystemVerilog assertions
      • You must be familiar with constrained random verification, coverage closure, release methodology, and revision control systems.

Keywords: SBT, Garland , Principal Verification Lead, Other , Garland, Texas

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