Senior Manager / Director, Plant Design (PD) - VLSI / SoC / ASIC Design - (Remote, US)
Company: Capgemini Engineering
Posted on: June 23, 2022
At Capgemini Engineering you will get to work on industry
leading VLSI technologies and craft innovative solutions to enable
industries/clients in diverse segments like (but not limited to)
AI/ML, Cloud, Datacenter, 5G, computers, communications, mobility,
automotive etc. You will work and partner with the best and
brightest in the field.As the Physical Design (PD) Lead for
Pathfinding, you will work with customers directly in the initial
phase of the engagement focusing on 'Tech Readiness' of the program
to be executed. This would include scoping the PD requirements from
customer and the sizing, resource estimates depending on technical
details, known execution risks and mitigations aligned with
customer. You should be able to lead the functional area (PD) and
represent Capgemini Engineering to the customer and vice versa.
Internally you will draw out the PD execution plan and work with
implementation leads to draft SOW, milestones. After the
Pathfinding/TR phase, you will own the 'PD' execution for the chip
to meet the spec/requirements as aligned with all the
stakeholdersYou will lead back end SoC team covering RTL to GDS
methodology, design convergence, and design quality for our
--- Contribute to and own large partitions, sub-chips, and/or full
chip from synthesis to place and route through all sign-off
including timing signoff, physical verification, EMIR signoff,
Formal Equivalence, and Low Power Verification.
--- Influence tools, flows, and overall design methodology in
design construction, signoff, and optimization with a data driven
--- Contribute to and own Floorplanning and design planning tasks
for large sub-chips/full chip.
--- Have close interaction with RTL team to help drive and resolve
design issues related to block closure.
--- Implement robust clock distribution solutions using appropriate
methods that meet design requirements.
--- Accurately plan out and clearly communicate block schedules and
risks through different project phases.
--- Make good independent technical trade-offs between power, area,
--- Provide technical input and collaborate across teams to produce
the best solution possible Preferred Qualifications:
--- 12-15+ years of experience in Physical Design
--- Great communication, collaboration and teamwork skills and
ability to contribute to diverse and inclusive teams.
--- Strong fundamentals in VLSI design
--- Experience in taping out chips in advanced process nodes is
--- Strong problem-solving and data analysis skills
--- Strong skills using scripting languages such as Perl, TCL,
--- Proven track record of implementing designs through synthesis,
Floorplanning, place and route, extraction, timing, and physical
--- Understanding of constraints generation, STA, timing
optimization, and timing closure.
--- Experience in EDA tools such as Primetime, StarRC, Genus,
Innovus, Design Compiler, ICC/ICC2.
--- Understanding of design tradeoffs for power, performance, and
--- Proficient understanding of CTS and different clock building
--- Experience with multi-voltage, multi-clock, multi-domain, and
low power designs. Education:BSEE., in
Electronics/Telecommunication OR Electrical OR Computer
Keywords: Capgemini Engineering, Garland , Senior Manager / Director, Plant Design (PD) - VLSI / SoC / ASIC Design - (Remote, US), Professions , Garland, Texas
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